System in a Package

System in a Package (SiP) is a functional sub-system using advanced semiconductor packaging. Typically it will contain two or more dissimilar die, i.e.,the combination of a processor, gate array, RAM and NV memories can be combined with other components such as passives, filters, mechanical parts, voltage regulators, etc.

These are assembled on an interposer or substrate to create a customized, integrated product for specific application. Within the SiP, the designer can utilize bare die (wire bond or flip chip); FBGA/CSP packaged devices; stacked die; stacked packages.

Multi-chip packages are lower cost functional blocks, typically memory, and making use of the established packaging and assembly infrastructure. Multi-chip packages can be viewed as standard single-chip packages, modified to accommodate the multiple ICs and passive components to provide the user with much higher density and integration.

Both technologies own broad application opportunities across many market segments including consumer electronics, mobile phones, automotive, medical, computer, telecom and defense-aerospace. WEDC focuses their design, assembly and test resources on the defense-aerospace segment, the data communication segment and high-end computer segment.

System in a package in combination with BGA technology is viewed as part of the solution set for the gap between silicon I/O density and performance and the material capabilities of the package and board/substrate.

WEDC provides a one-stop, on-shore source for concept analysis, mcm design services, assembly and test of high density semiconductor packaging for the military and other mission critical market applications.

View our System in a Package (SiP) brochure