Microsemi’s family of SSRAM based Multi-Chip Packages (MCPs) are designed to give our customers a high density memory solution that also meets the wide data widths necessary for their applications. These high speed memories use synchronous inputs controlled by a positive-edge-triggered single-clock input including addresses, data and control.
Starting at a density of 2MB (16Mb) in x32 and x72 data width configurations these SSRAM memories provide many benefits such as space savings versus single die packages, reduced I/O routing, reduced component count and placements, and extended temperature range testing including industrial and military.
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NBL SSRAM MCP
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| Density |
Organization |
Part Number |
Speed |
Volt |
Package |
Temp |
PDF |
| 4MB |
512Kx72 |
WEDPZ512K72V-XBX |
100-150 MHz |
3.3 |
152 PBGA |
C,I,M |
Datasheet
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SSRAM MCP
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| Density |
Organization |
Part Number |
Speed |
Volt |
Package |
Temp |
PDF |
| 16Mb |
512Kx32 |
WED2DL32512V |
133-200 MHz |
3.3 |
119 PBGA |
C, I |
Datasheet
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| 16Mb |
256Kx72 |
WEDPY256K72V-XBX |
100-200 MHz |
3.3 |
159 BGA |
C,I,M |
Datasheet
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Ver.sr.ssrmul-2
