Our family of DDR2 SDRAM based Multi-Chip Packages (MCPs) are designed to give our customers a high density memory solution that also meets the wide data widths necessary for their applications. These high speed memories use a 4ns-prefetch architecture with an interface that allows two data words to be transmitted per clock cycle.
With densities up to 1Gbyte in x64 and x72 data width configurations, these DDR2 memories provide many benefits, such as: space savings versus single die packages, including CSPs; reduced I/O routing; reduced component count and placements; and extended temperature range testing, including industrial and military.
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DDR2 SDRAM
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| Organization |
Part Number |
Speed |
Volt |
Package |
PDF |
| 32Mx64 |
W3H32M64E-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
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| 32Mx72 |
W3H32M72E-XSB2X |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
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| 64Mx16 |
W3H64M16E-XBX |
400-667 Mbs |
1.8 |
79 PBGA |
Datasheet
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| 64Mx64 |
W3H64M64E-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
|
| 64Mx72 |
W3H64M72E-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
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| 128Mx72 |
W3H128M72E-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
|
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DDR2 SDRAM Single-Rank
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| Organization |
Part Number |
Speed |
Volt |
Package |
PDF |
| 32Mx64 |
W3H32M64EA-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
|
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Registered DDR2 SDRAM
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| Organization |
Part Number |
Speed |
Volt |
Package |
PDF |
| 128Mx72 |
W3H128M72ER-XNBX |
400-667 Mbs |
1.8 |
255 PBGA |
Datasheet
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Ver.sd.ddr2-2
