Our family of DDR2 SDRAM based Multi-Chip Packages (MCPs) are designed to give our customers a high density memory solution that also meets the wide data widths necessary for their applications. These high speed memories use a 4n-prefetch architecture with an interface that allows two data words to be transmitted per clock cycle.
Starting at a density of 256MB (2Gb) in x64 and x72 data width configurations these DDR2 memories provide many benefits such as; space savings versus single die packages including CSPs, reduced I/O routing, reduced component count and placements, and extended temperature range testing including industrial and military.
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DDR2 SDRAM
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| Organization |
Part Number |
Speed |
Volt |
Package |
PDF |
| 32Mx64 |
W3H32M64E-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet Flyer
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| 32Mx72 |
W3H32M72E-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet Flyer
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| 64Mx64 |
W3H64M64E-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
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| 64Mx72 |
W3H64M72E-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
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| 128M x 72 |
W3H128M72E-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
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Registered DDR2 SDRAM
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| Organization |
Part Number |
Speed |
Volt |
Package |
PDF |
| 128M x 72 |
W3H128M72ER-XSBX |
400-667 Mbs |
1.8 |
208 PBGA |
Datasheet
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