Microsemi’s family of DDR SDRAM based Multi-Chip Packages (MCPs) is designed to give our customers a high density memory solution that also meets the wide data widths necessary for their applications. These high speed memories use a 2ns-prefetch architecture with an interface that allows two data words to be transmitted per clock cycle.
Starting at a density of 128MB (1Gb) in x16, x64 and x72 data width configurations these DDR memories provide many benefits, such as: space savings versus single die packages including CSPs, reduced I/O routing, reduced component count and placements, and extended temperature range testing including industrial and military.
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DDR SDRAM MCP
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| Density |
Organization |
Part Number |
Speed |
Volt |
Package |
PDF |
| 128MB |
64Mx16 |
W3E64M16S-XSBX |
200-333 Mb/s |
2.5 |
60 PBGA |
Datasheet
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| 128MB |
64Mx16 |
W3E64M16S-XNBX |
200-333 Mb/s |
2.5 |
60 PBGA, Thin |
Datasheet
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| 128MB |
16Mx64 |
W3E16M64S-XBX |
200-266 Mb/s |
2.5 |
219 PBGA |
Datasheet
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| 256MB |
32Mx64 |
W3E32M64SA-XBX |
200-333 Mb/s |
2.5 |
219 PBGA |
Datasheet
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| 256MB |
32Mx64 |
W3E32M64S-XBX |
200-333 Mb/s |
2.5 |
219 PBGA |
Datasheet
|
| 256MB |
32Mx64 |
W3E32M64S-XSBX |
200-333 Mb/s |
2.5 |
208 PBGA |
Datasheet
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| 128MB |
16Mx72 |
W3E16M72S-XBX |
200-266 Mb/s |
2.5 |
219 PBGA |
Datasheet
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| 256MB |
32Mx72 |
W3E32M72S-XBX |
200-333 Mb/s |
2.5 |
219 PBGA |
Datasheet
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| 256MB |
32Mx72 |
W3E32M72S-XSBX |
200-333 Mb/s |
2.5 |
208 PBGA |
Datasheet
|
| 512MB |
64Mx72 |
W3E64M72S-XSBX |
200-333 Mb/s |
2.5 |
219 PBGA |
Datasheet
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|
Registered DDR SDRAM MCP
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| Density |
Organization |
Part Number |
Speed |
Volt |
Package |
PDF |
| 128MB |
16Mx72 |
W3E16M72SR-XBX |
200-250 Mb/s |
2.5 |
219 PBGA |
Datasheet
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| 256MB |
32Mx72 |
W3E32M72SR-XSBX |
200-266 Mb/s |
2.5 |
208 PBGA |
Datasheet
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Ver.sd.sddr-2
